1. Field of the Invention
Embodiments of the invention relate to a semiconductor device and a related fabrication method. In particular, embodiments of the invention relate to a semiconductor device comprising a gate electrode comprising upper and lower silicon patterns, wherein the upper silicon pattern has the same crystal structure as a lower silicon pattern, and a related method of fabrication.
This application claims priority to Korean Patent Application No. 2006-14784, filed on Feb. 15, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
In general, a semiconductor memory device can be classified as a volatile memory device or a nonvolatile memory device. Volatile memory devices, such as dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices, have relatively high data input and output speeds; however, data stored in a volatile memory device is lost when the power supplied to the device is turned OFF. On the other hand, a nonvolatile memory device, such as a flash memory device, is able to maintain the data stored in the device even when the power supplied to the device is turned OFF. Volatile and nonvolatile semiconductor memory devices each include multiple transistors.
Figure (FIG.) 1 is a schematic cross-sectional view of a conventional MOS transistor. Referring to FIG. 1, a gate insulating layer 30 and a gate electrode 40 are disposed on an active region 15 of a semiconductor substrate 10. Active region 15 is defined by a device isolation layer 20.
As a design rule decreases, an aspect ratio of gate electrode 40 increases, so the likelihood that defects such as voids were generated inside gate electrode 40 when it was formed becomes relatively high.
FIGS. 2 and 3 are schematic cross-sectional views of a conventional non-volatile memory device. Referring to FIG. 2, device isolation layer 20, which defines active region 15, is disposed on a predetermined region of semiconductor substrate 10. A floating gate electrode 40 is disposed on active region 15, and gate insulating layer 30 is disposed between floating gate electrode 40 and active region 15. A control gate electrode 60 is disposed on active region 15, device isolation layer 20, and floating gate electrode 40. In addition, a gate insulating layer 50 is disposed between floating gate electrode 40 and control gate electrode 60. Control gate electrode 60 is used as a word line for selecting a predetermined cell of a cell array having a plurality of memory cells.
Referring to FIG. 2, surfaces of floating gate electrode 40 and control gate electrode 60 face each other with gate insulating layer 50 interposed between those surfaces. A coupling ratio between floating gate electrode 40 and control gate electrode 60 is proportional to the area of the surfaces of electrodes 40 and 60 facing each other. Since a width d1 of floating gate electrode 40 and an interval d2 between floating gate electrodes 40 should be reduced in order to achieve a high degree of integration in the device of FIG. 2, the respective heights of floating gate electrodes 40 should be increased in order to increase the area of the surfaces facing one another (i.e., to increase the coupling ratio). However, increasing the respective heights of floating gate electrodes 40 may cause electrical interference to be generated because increasing the respective heights of floating gate electrodes 40 increases the respective areas of the surfaces of adjacent floating gate electrodes 40 that face one another and increases the respective areas of the surfaces of a floating gate electrode 40 and a control gate electrode 60 (i.e., a word line) that face one another. The generation of electrical interference is a problem because electrical interference may change data stored in a memory cell.
A proposed solution to the problems discussed above is using a floating gate electrode having a “T”-shaped cross-section. Referring to FIG. 3, floating gate electrode 41 includes a lower polysilicon pattern 42 and an upper polysilicon pattern 44. The height of floating gate electrode 41 of FIG. 3 is greater than the height of floating gate electrode 40 of the memory device illustrated in FIG. 2, but upper polysilicon pattern 44 is narrower than lower polysilicon pattern 42, and an interval between adjacent upper polysilicon patterns 44 is relatively large, which can reduce electrical interference. However, many problems may occur when forming the memory device illustrated in FIG. 3.
FIGS. 4A and 4B are cross-sectional views illustrating a method for forming the conventional nonvolatile memory device illustrated in FIG. 3.
Referring to FIGS. 4A and 4B, a device isolation layer 20 defining an active region 15 is formed on a semiconductor substrate having a cell region A and a peripheral region B. Gate insulating layers 30 and 35 and lower polysilicon patterns 42 and 47 are formed on active region 15. Molding spacers 75 covering edges of upper surfaces of lower polysilicon patterns 42 and 47 are formed adjacent to upper sidewalls of device isolation layer 20. Upper polysilicon patterns 44 and 49 are formed on portions of lower polysilicon patterns 42 and 47 that are exposed between molding spacers 75. Thus, a floating gate electrode 41 is formed in cell region A, and a peripheral circuit gate pattern 45 is formed in peripheral region B. Because an interval between molding spacers 75 in cell region A is relatively narrow, upper polysilicon pattern 44 may not be formed uniformly. For example, defects such voids may be generated inside upper polysilicon pattern 44 when it is formed. As a design rule decreases, the problem just described may occur frequently. In addition, because an interval between pillar-shaped spacers 75 in peripheral region B is large, upper polysilicon pattern 49 is formed having a “U” shape. That is, edge portions of upper polysilicon pattern 49 are thicker than a central portion of upper polysilicon pattern 49.
Referring to FIG. 4B, after device isolation layer 20 is etched (i.e., recessed), a preliminary gate insulating layer 51 (not shown) and a control gate conductive layer 61 (not shown) are formed on semiconductor substrate 10. Subsequently, an etching process for patterning control gate conductive layer 61 and preliminary gate insulating layer 51 is performed to form a control gate electrode and an inter-gate insulating layer. While the etching process is performed, lower polysilicon pattern 47 in peripheral region B may be etched excessively and thus active region 15 may be etched (i.e., pits may be formed in active region 15). That is, because the edge portions of upper polysilicon pattern 49 are thicker than the central portion of upper polysilicon pattern 49, when upper polysilicon pattern 49 is etched, the central portion of upper polysilicon pattern 49 is etched away completely before the edge portions of upper polysilicon pattern 49 are etched away completely. Accordingly, a portion of lower polysilicon pattern 47 disposed under the central portion of upper polysilicon pattern 49 may be excessively etched, and thus active region 15 disposed under the etched portion of lower polysilicon pattern 47 may be etched (i.e., pits may be formed in that active region 15).
The problems described above may negatively affect an operational characteristic(s) and the reliability of a semiconductor device.